In computer and information processing systems, various integrated circuit chips must communicate digitally with each other over common buses. The differential sense amplifier is well known to provide a fast bit-line sensing mechanism in CMOS (complementary metal-oxide semiconductor) memory circuits such as SRAM (static random access memory), ROM (read only memory), PROM (programmable read only memory), and register files.
Differential sense amplifiers detect the difference between two input signals, referred to as the differential inputs. Typically, these input signals are a received signal and the inverse of the received signal. The differential sense amplifier senses the difference between the two input signals and determines the state of the received signal. Differential sense amplifiers have the advantage of good sensitivity, i.e., almost zero setup time and a specific hold time.
Differential sense amplifiers provide full-swing output signals by sensing small voltage (or current) differences between the dual input signals. As can be seen in FIG. 1, a differential sense amplifier (10) includes cross-coupled pmos transistors (12) and (14) and nmos transistors (16) and (18). These cross-coupled transistors (12), (14), (16), (18) are connected to reference voltage (VDD) and enabled using transistor (28). Transistor (28) is also connected to ground and receives the sense amplifier enable control signal (sae). The input bit-line signals (bt) and (bt_n) are received by the differential sense amplifier (10) through transistors (20) and (22) respectively. These transistors (20) and (22) also receive a column select signal (cs) and are coupled to the cross-coupled transistors (12), (14), (16), (18).
When enabled by transistor (28), there is a differential voltage across the cross-coupled transistors (12), (14), (16), (18). The cross-coupled transistors (12), (14), (16), (18) amplify even small voltage differences between the inputs because of the positive feedback mechanism employed. Thus, a full swing (0 to VDD, or vice-versa) can be realized on the differential output lines (out) and (out_n). Differential sense amplifiers are well suited for large memory circuits, whose number of entries is around 128 or more, because the area overhead of the differential sense amplifier is relatively small compared to the whole circuit area in such cases.
The output signals (out) and (out_n) are fed out of the differential sense amplifier (10) through inverters (24) and (26) respectively. Additionally, a recovery circuit (30) may be included at the inputs (bt) and (bt_n). Recovery circuit (30) is made up of two p-channel transistors (31) and (33) that are coupled together and connected to a reference voltage VDD. The recovery circuit (30) is for precharging to VDD the lines on which input bit-line signals (bt) and (bt_n) are received. This precharging readies the lines for evaluation of the input signals (bt) and (bt_n). When the evaluation starts, the recovery circuit signal (rec) shuts off the precharge path from VDD.
In general, in accordance one or more embodiments of the present invention, a single-input/dual output sense amplifier comprises cross-coupled transistors connected to a reference voltage; a first input transistor and a second input transistor connected the cross-coupled transistors; the first input transistor coupled to a single input bit-line; the second input transistor coupled to a reference voltage; an inverter receiving the input bit-line signal and outputting a complement of the input bit-line signal; a control circuit coupled to the second input transistor and receiving the complement of the input bit-line signal; and dual differential outputs.
In general, in accordance one or more embodiments of the present invention, a method of producing dual differential output signals from a single input signal comprises receiving a single input bit-line signal; inverting the received single input bit-line signal to produce the complement of the received single input bit-line signal; controlling the charging and discharging of a reference node based on the complement of the received input bit-line signal; and outputting dual differential output signals.
In general, in accordance one or more embodiments of the present invention, an apparatus for producing dual differential output signals from a single input signal comprises means for receiving a single input bit-line signal; means for inverting the received single input bit-line signal to produce the complement of the received single input bit-line signal; means for controlling the charging and discharging of a reference node based on the complement of the received input bit-line signal; and means for outputting dual differential output signals
In general, in accordance one or more embodiments of the present invention, a single-input/dual output sense amplifier comprises cross-coupled transistors connected to a reference voltage and enabled by an enable transistor, the cross-coupled transistors comprising a first pmos transistor and second pmos transistor and a first nmos transistor and second nmos transistor; the enable transistor connected to ground and receiving a sense amplifier enable control signal; a first input transistor and a second input transistor connected the cross-coupled transistors and receiving a column select signal; the first input transistor coupled to a single input bit-line; the second input transistor coupled to a reference voltage; an inverter receiving the input bit-line signal and outputting a complement of the input bit-line signal; a control circuit coupled to the second input transistor and receiving the complement of the input bit-line signal and the column select signal; and dual differential outputs.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.